1. Field of the Invention
The present invention relates to semiconductor integrated circuit structures and, in particular, to a novel MOSFET gate design that includes short/narrow gate cells that are connected both in parallel and in series in order to increase the device current derive, while maintaining the overall device performance characteristics of larger geometry devices, and while minimizing short channel effects (SCE) and narrow channel effects (NCE).
2. Discussion of the Related Art
It has been shown that MOSFET transistors show degraded performance due to enhanced short channel effects (SCE) as the transistors are made shorter. For example, the threshold voltage of an N-channel MOSFET transistor gets smaller as the channel length of the transistor is made shorter. In general, the overall performance characteristics of a MOSFET device become impaired as a result of severe short channel effects if the device is made shorter than that provided by currently available technology.
The channel width of a MOSFET device has a similar effect on the transistor characteristics, but in the opposite sense. That is, the threshold voltage of an N-channel MOSFET transistor becomes larger when the channel width is made narrower.
H.S. Lee, xe2x80x9cAn Analysis of the Threshold Voltage for Short Channel IGFETsxe2x80x9d, Solid State Electronics, 1973, vol. 15, pgs. 1407-1417, teaches that when the MOSFET transistor channel gate is made short as well as narrow, the two threshold voltage shift effects, i.e. SCE and NCE, have a compensating tendency. Also, the threshold voltage of such a short/narrow device can actually improve and may approach that of a larger geometry device.
The present invention provides a novel MOSFET gate design. The new gate design includes short/narrow gate cells that are connected in parallel and in series in order to increase the device current derive. The overall device performance characteristics look like those of a larger geometry device, with minimal short channel effects and narrow channel effects.
More specifically, a short/narrow high performance MOS transistor structure in accordance with the present invention includes a semiconductor substrate well having a first conductivity type. The substrate well is surrounded by shallow trench isolation (STI), typically silicon dioxide. A first linear sequence of diffusion regions having a second conductivity type is formed in the semiconductor substrate. Each diffusion region in the first sequence is spaced-apart from a prior diffusion region in the first sequence to define a substrate channel region between adjacent diffusion regions. A second linear sequence of diffusion regions having,a second conductivity is also formed in the semiconductor substrate. As in the case of the first linear sequence, each diffusion region in the second sequence is spaced-apart from a prior diffusion region in the second sequence to define a substrate channel region therebetween. A region of shallow trench isolation dielectric material is formed in the semiconductor substrate between the first linear sequence and its associated substrate channel regions and the second sequence of diffusion regions and its associated substrate channel regions. The region of dielectric material provides electrical isolation between the first and second linear diffusion region sequences. Each substrate channel region of the first linear sequence corresponds to a substrate channel region of the second linear sequence to define a plurality of channel region pairs. In further accordance with the invention, a conductive gate electrode is provided that includes a plurality of spaced-apart gate electrode fingers. Each of the gate electrode fingers is connected to a common gate electrode portion. Each of the gate electrode fingers extends over an associated channel region pair and is separated therefrom by intervening dielectric material. The diffusion regions in the first and second linear diffusion region sequences are alternately connected to the source and drain electrodes of the device, resulting in short/narrow gate cells that are connected both in parallel and in series, thereby increasing the device current derive while maintaining well controlled device characteristics.